Intel Patent Hints at Plans for Multi-Chip-Module GPUs

The technology giant’s patent detailing the construction of a multi-chip module with up to six graphics processing units could be a big step towards even more powerful GPUs.

A recent patent by Intel hints at plans for multi-chip-module GPUs. This will allow the company to create smaller, more efficient graphics cards that have a lower power draw.

Image credit: Intel

NVIDIA and AMD aren’t the only companies working on multi-chip-module (MCM) GPU architectures for their next-generation graphics cards. Intel also seems to be flirting with the notion of having several GPU modules function inside a single package as part of a new design that might offer faster performance, lower manufacturing costs, and other advantages, according to a recent patent application seen by Twitter user Underfox. “Position-Based Rendering Apparatus and Method for Multi-Die/GPU Graphics Processing” is the title of the patent application.

Intel has been granted a patent for a For multi-die/GPU graphics processing, a position-based rendering apparatus and technique are proposed.

MCM GPUs from Intel are on the way…

https://t.co/GIkfwrXGzV for more information pic.twitter.com/sXGt9nbJ1S

— February 3, 2022, Underfox (@Underfox3)

US20210272349 is a patent application filed in the United States (FPO)

For multi-die/GPU graphics processing, a position-based rendering apparatus and technique are proposed.
A technique that includes partitioning a picture frame into a number of tiles and allocating a non-overlapping subset of the tiles to each of a number of graphics processors [et al.].
A graphics processing system includes: a plurality of graphics processors, each of which is assigned a non-overlapping subset of a plurality of tiles in an image frame, each of which is integrated on a separate semiconductor die and includes a graphics pipeline for rendering the assigned subset of tiles [et al.].

(Tom’s Hardware) Intel Patent Confirms Work On Multi-Chip-Module GPUs

[…] The MCM as a whole approach is framed by the business as a necessary step in guiding silicon designers away from the difficulties of manufacturability, scalability, and power delivery that result from growing die sizes in the never-ending quest for performance.
Intel seems to be considering combining tile-based checkerboard rendering (a capability included in today’s GPUs) with distributed vertex position computation (out of the initial frame pass).
[…] it enables for systems with numerous graphics processors or only pieces of graphics processors running in tandem.